7 计数器&存储器&综合

VL50 简易秒表

`timescale 1ns/1ns

module count_module(
    input clk,
    input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
    );
    
    always@(posedge clk or negedge rst_n)
    begin
        if(~rst_n)
            second <= "d0;
        else if(minute == 60)
            second <= second;
        else
            second <= (second<60)?second + 1:1;
    end
    
    always@(posedge clk or negedge rst_n)
    begin
        if(~rst_n)
            minute <= "d0;
        else if(second == 60)
            minute <= minute + 1;
    end
    
endmodule