09 Latches and Flip-Flops

Dff

这一节终于开始时序电路了。首先是一个用的最多的D触发器。

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//

    // Use a clocked always block
    //   copy d to q at every positive edge of clk
    //   Clocked always blocks should use non-blocking assignments
    always@(posedge clk)
    begin
       q <= d; 
    end

endmodule