8 企业真题

VL59 根据RTL图编写Verilog程序

这题比较简单，照着写就好了。

`timescale 1ns/1ns

module RTL(
    input clk,
    input rst_n,
    input data_in,
    output reg data_out
    );
    reg data_in_reg;
    always@(posedge clk)
    begin
        if(~rst_n)
        begin
            data_in_reg <= 1"b0;
            data_out <= 1"b0;
        end
        else begin
            data_in_reg <= data_in;
            data_out <= data_in&~data_in_reg;
        end
    end

endmodule