3 时序逻辑

VL21 根据状态转移表实现时序电路

写一个简单的Moore状态机就可以了，太短就懒得写三段式了。

`timescale 1ns/1ns

module seq_circuit(
      input                A   ,
      input                clk ,
      input                rst_n,
 
      output   wire        Y   
);

reg [1:0]state;
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
        state <= 0;
    else begin
        case(state)
        0:state <= A?3:1;
        1:state <= A?0:2;
        2:state <= A?1:3;
        3:state <= A?2:0;
        endcase
    end
end
assign Y = (state == 2"b11);
endmodule